One device, multiple tasks:
Begin of Project: Oktober 2016
Aufwand für Nachbau:
Christian Meiners, email@example.com
Main Ideas based on prototypes an schematics from Klaus Zipfel.
current from LEM ultrastab is transduced to voltage using a shunt and a diffamp. A error signal is generated by adding a iverted set signal. This error signal is fed into two PIDs. PID A has A Sample and hold option which works as follows: the PID output is fed into the S&H circuit, once activated the S&H outputs a constant voltage which was previously the PID output signal. At the same time the difference between this constant voltage and the actual PID output voltage is fed as a new error signal to the PID input.
In progress, Hammond for 160*100 mm, Height?
Up to now only PID A is populated (exept D) after Hacking the logic at the S&H IC, it works as expected. after switching in hold mode, the current seems to be a bit lower than the initial setpoint. this might be caused by the big hold capacitor. Maybe after 0.5 sec. it is not entirely loaded. The hold time seems to be huge, after 30s there is almost no change visible, seems to be a fraction of a Millivolt. So it might be an option to change the Cap to a smaller one, leading to a smaller hold time, but a more precise hold value.
The idea of having the current on for a longer time before switching to hold mode didn't rally help, so it doesn't seem to be an problem related to the loading curve of the hold cap. after a hold time of ~4 minutes, the current monitor voltage dropped from ~39.6 mV to 39 mV.
|ULTRASTAB (D-SUB)||analog current (differential)||current input from current transducer,\\can be modified to differential voltage input.|
|Current set||analog voltage (differential)||current setpoint|
|enable||digital voltage (optocoupled)|| high: PIDs enabled, outputs active
low: disabled, MOSFET out turned to zero.
|S&H||digital voltage (optocoupled)|| high: S&H active, PID A holds voltage on disable
low: S&H diasbled, PID A returns to zero on disable
|interlock||digital voltage (optocoupled)|| high: device operational,
low: all outputs off, PIDs return to zero
|1||Current monitor output reference|| pin 1 (right): normal gnd
pin 3 (left): clean gnd
|2||MOSFET output selection|| pin 1 (right): PID B (without S&H)
pin 3 (left): PID A (with S&H)
|3||Enable Input usage|| pin 1 (left): connect enable in
pin 3 (right): connect to gnd, permanent enable
|4||ULTRASTAB interlock usage|| pin 1 (top): ULTRASTAB interlock used
pin 3 (bottom): ULTRASTAB interlock ignored
|5||External Interlock usage|| pin 1 ( left): ext. interlock used
pin 3 (right): ext. interlock ignored
|6||Sample and Hold usage|| pin 1 (bottom): S&H input connected
pin 3 (top): S&H permanently enabled
No Jumper: S&H permanently disabled
|Leiterplatte||1x||??.?? €||€||1/n von XXX EUR|
|R,C||??x||0.02 €||€||Bauform 0805|
|Bestückung||??.00 €||bei SRM|
Was für die nächste Version zu tun ist: (: verworfen, : in Arbeit, : im Schaltplan, aber noch nicht im Layout, : erledigt)